1. Field of the Invention
This invention relates to digital communication systems, and more particularly to bidirectional digital data transmission via a single transmission medium.
2. Description of the Relevant Art
Digital electronic devices typically communicate via electrical signals (e.g., voltage and/or current) driven upon electrical conductors (e.g., metal wires). As the operating frequencies (i.e., xe2x80x9cspeedsxe2x80x9d) of digital electronic devices increase, electrical conductors used to route signals between components (i.e., signal lines) begin to behave like transmission lines. Transmission lines have characteristic impedances. If the input impedance of a receiving device connected to a transmission line does not match the characteristic impedance of the transmission line, a portion of an incoming signal is reflected back toward a sending device. Such reflections cause the received signal to be distorted. If the distortion is great enough, the receiving device may erroneously interpret the logical value of the incoming signal.
Binary digital signals typically have a low voltage level associated with a logic low (i.e., a logic xe2x80x9c0xe2x80x9d), a high voltage level associated with a logic high (i.e., a logic xe2x80x9c1xe2x80x9d), xe2x80x9crise timesxe2x80x9d associated with transitions from the low voltage level to the high voltage level, and xe2x80x9cfall timesxe2x80x9d associated with transitions from the high voltage level to the low voltage level. A signal line behaves like a transmission line when the signal rise time (or signal fall time) is short with respect to the amount of time required for the signal to travel the length of the signal line (i.e., the propagation delay time of the signal line). As a general rule, a signal line begins to behave like a transmission line when the propagation delay time of the signal line is greater than about one-quarter of the signal rise time (or signal fall time).
Resistive xe2x80x9cterminationxe2x80x9d techniques are often applied to transmission lines, and signal lines long enough to behave like transmission lines, in order to reduce reflections and the resultant signal distortion. One or more electrically resistive elements may be inserted between each sending device and the signal line (i.e., transmission line) in order to cause the effective output impedances of the sending devices to more closely match the characteristic impedance of the transmission line. Similarly, one or more electrically resistive elements may be inserted between each receiving device and the transmission line in order to cause the effective input impedances of the receiving devices to more closely match the characteristic impedance of the transmission line.
Various techniques exist which allow signals to travel in opposite directions along a single electrical path (i.e., bidirectional data transmission). Such bidirectional data transmission techniques may be employed to reduce the total number of electrical conductors required in digital communication systems.
FIG. 1 is a diagram of an exemplary digital communication system 10 employing a bidirectional data transmission technique. Digital communication system 10 includes a first communication device 12a and a second communication device 12b connected to opposite ends of a transmission line 14. Communication devices 12a and 12b are synchronized to drive data signals upon transmission line 14 during alternate periods of the clock signal. Transmission line 14 includes at least two electrical conductors, and may be, for example, a single wire routed above an electrically conductive ground plane, a coaxial cable, or a pair of wires twisted together (i.e., a twisted pair of wires). Communication device 12a includes an input/output (I/O) driver 16a and an I/O terminal 18a connected to one end of transmission line 14. Communication device 12b includes an I/O driver 16b and an I/O terminal 18b connected to the other end of transmission line 14. I/O drivers 16 include circuitry for driving electrical signals upon the respective I/O terminals 18, and for receiving input signals from I/O terminals 18. I/O drivers 16a and 16b operate synchronously in response to a periodic clock signal. Communication devices 12a and 12b may be coupled to receive the clock signal via a clock signal line, or may include circuitry to generate and synchronize two separate clock signals.
FIG. 2 is a diagram illustrating the cyclic nature of the bidirectional data transmission technique employed by digital communication system 10. Each period of the clock signal begins with a transition from a first voltage level xe2x80x9cV1xe2x80x9d to a second voltage level xe2x80x9cV2xe2x80x9d, where V2 greater than V1 (i.e., a rising edge of the clock signal). During a first period of the clock signal (i.e., a first clock cycle) 22, communication device 12a drives a data signal upon transmission line 14 via I/O driver 16a and I/O terminal 18a, and communication device 12b receives the data signal via I/O terminal 18b and I/O driver 16b. During a second clock cycle 24 immediately following first clock cycle 22, communication device 12b drives a data signal upon transmission line 14 via I/O driver 16b and I/O terminal 18b, and communication device 12a receives the data signal via I/O terminal 18a and I/O driver 16a. The data transmission cycle repeats itself as shown in FIG. 2 with communication devices 12a and 12b alternately driving and receiving data.
Transmission line 14 has a characteristic impedance xe2x80x9cZOxe2x80x9d. In order to reduce signal reflections within transmission line 14, I/O drivers 16a-b drive respective I/O terminals 18a-b with an output resistance equal to ZO, and electrically couple I/O terminals 18a-b to the second voltage level through an electrical resistance equal to ZO while in a receive mode.
FIG. 3 is a timing diagram illustrating exemplary voltage levels within digital communication system 10 during employment of the bidirectional data transmission technique. At a time xe2x80x9ct1xe2x80x9d in FIG. 3, the clock signal transitions from the first voltage level xe2x80x9cV1xe2x80x9d to the second voltage level xe2x80x9cV2xe2x80x9d, beginning a first clock signal period in which communication device 12a drives data upon transmission line 14 and communication device 12b receives the data. During the first clock signal period, communication device 12a is to drive the first voltage level xe2x80x9cV1xe2x80x9d (e.g., a logic xe2x80x980xe2x80x99) upon transmission line 14 via I/O driver 16a and I/O terminal 18a. 
I/O drivers 16a-b cannot drive respective I/O terminals 18a-b immediately, and an output delay time xe2x80x9ctOUTxe2x80x9d results. At a time xe2x80x9ct2xe2x80x9d, delayed from time xe2x80x9ct1xe2x80x9d by xe2x80x9ctOUTxe2x80x9d, I/O driver 16b electrically couples I/O terminal 18b to the second voltage level, and I/O driver 16a drives I/O terminal 18a. As the output resistance of driver 16a is equal to the characteristic impedance xe2x80x9cZOxe2x80x9d of transmission line 14, the signal launched upon transmission line 14 by communication device 12a via I/O terminal 18a at time xe2x80x9ct2xe2x80x9d has a voltage level midway between xe2x80x9cV1xe2x80x9d and xe2x80x9cV2xe2x80x9d.
A propagation delay time xe2x80x9ctPROPxe2x80x9d is required for a signal to travel from one end of transmission line 14 to the other. At time xe2x80x9ct3xe2x80x9d, delayed from time xe2x80x9ct2xe2x80x9d by xe2x80x9ctPROPxe2x80x9d, the signal launched upon transmission line 14 by communication device 12a at time xe2x80x9ct2txe2x80x9d arrives at I/O terminal 18b, and I/O terminal 18b assumes the voltage level midway between xe2x80x9cV1xe2x80x9d and xe2x80x9cV2xe2x80x9d.
I/O driver 16b compares the voltage level present upon I/O terminal 18b to a reference voltage having a value greater than midway between xe2x80x9cV1xe2x80x9d and xe2x80x9cV2xe2x80x9d (e.g., two-thirds the difference between xe2x80x9cV1xe2x80x9d and xe2x80x9cV2xe2x80x9d). At a time xe2x80x9ct4xe2x80x9d following xe2x80x9ct3xe2x80x9d, the clock signal transitions from xe2x80x9cV1xe2x80x9d to xe2x80x9cV2xe2x80x9d, beginning a second clock signal period. At time xe2x80x9ct4xe2x80x9d the voltage level present upon I/O terminal 18b is less than the reference voltage, and I/O driver 16b produces and provides voltage level xe2x80x9cV1xe2x80x9d (e.g., a logic xe2x80x980xe2x80x99) to communication device 12b as the input data signal received from communication device 12a. 
During the second clock signal period beginning at time xe2x80x9ct4xe2x80x9d, communication device 12b drives data upon transmission line 14 and communication device 12a receives the data. Specifically, communication device 12b is to drive the first voltage level xe2x80x9cV1xe2x80x9d (e.g., a logic xe2x80x980xe2x80x99) upon transmission line 14 via I/O driver 16b and I/O terminal 18b. As I/O drivers 16a-b cannot drive respective I/O terminals 18a-b immediately, output delay time xe2x80x9ctOUTxe2x80x9d results. At a time xe2x80x9ct5xe2x80x9d, delayed from time xe2x80x9ct4xe2x80x9d by xe2x80x9ctOUTxe2x80x9d, I/O driver 16b drives I/O terminal 18a to the first voltage level xe2x80x9cV1xe2x80x9d, and I/O driver 16b electrically couples I/O terminal 18a to the second voltage level xe2x80x9cV2xe2x80x9d.
The signal launched upon transmission line 14 by communication device 12b at time xe2x80x9ct5xe2x80x9d has the first voltage level xe2x80x9cV1xe2x80x9d. At a time xe2x80x9ct6xe2x80x9d, delayed from time xe2x80x9ct5xe2x80x9d by xe2x80x9ctPROPxe2x80x9d, the signal, launched upon transmission line 14 by communication device 12b at time xe2x80x9ct5xe2x80x9d arrives at; I/O terminal 18a. As I/O driver 16a electrically couples I/O terminal 18a to xe2x80x9cV2xe2x80x9d through an electrical resistance equal to ZO, and I/O driver 16b drives I/O terminal 18b to xe2x80x9cV1xe2x80x9d through an electrical resistance equal to ZO, the voltage levels at I/O terminals 18a and 18b stabilize to the voltage level midway between xe2x80x9cV1xe2x80x9d and xe2x80x9cV2xe2x80x9d at time xe2x80x9ct6xe2x80x9d.
I/O driver 16a compares the voltage level present upon I/O terminal 18a to the reference voltage. At a time xe2x80x9ct7xe2x80x9d following xe2x80x9ct6xe2x80x9d, the clock signal transitions from xe2x80x9cV1xe2x80x9d to xe2x80x9cV2xe2x80x9d, beginning a third clock signal period. At time xe2x80x9ct7xe2x80x9d the voltage level present upon I/O terminal 18a is less than the reference voltage, and I/O driver 16a produces and provides voltage level xe2x80x9cV1 xe2x80x9d (e.g., a logic xe2x80x980xe2x80x99) to communication device 12a as the input data signal received from communication device 12b. 
It would be beneficial to have a data transmission system and method allowing each of a pair of communication devices coupled to a transmission line to both transmit and receive data during each cycle of a clock signal (i.e., simultaneous bidirectional data transmission). Such a data transmission system would potentially double the data transmission rate over the transmission line.
The problems outlined above are in large part solved by a digital communication system implementing a data transmission method which allows each of a pair of communication devices coupled to a transmission line to both transmit and receive data during each cycle of a clock signal (i.e., simultaneous bidirectional data transmission). The digital communication system includes first and second communication devices coupled to opposite ends of a transmission line. Both the first and second communication devices operate in response to a periodic clock signal. The first and second communication devices simultaneously: (i) drive an output data signal upon the transmission line during a first portion of a period of the clock signal, and (ii) receive an input signal from the transmission line during a remainder of the period of the clock signal. The communication devices may be coupled to receive the clock signal via a clock signal line, or may include circuitry to generate and synchronize two separate clock signals.
The first and second communication devices may include an input/output (I/O) driver circuit. Each I/O driver circuit may include an I/O node operably coupled to the transmission line, an output driver section coupled to the I/O node, and an input section coupled to the I/O node. The output driver section may receive the output data signal from the corresponding communication device and drive the output data signal upon the I/O node during the first portion of the clock signal period. The input section may receive the input signal from the I/O node during the remainder of the clock signal period, produce an input data signal based upon the input signal, and provide the input data signal to the corresponding communication device.
The output driver section may also receive the clock signal from the corresponding communication device. During the first portion of the clock signal period, the output driver section may operate in a xe2x80x9cdrivexe2x80x9d mode, and may drive the output data signal upon the I/O node. During the remainder of the clock signal, the output driver section may operate in a xe2x80x9cterminatexe2x80x9d mode, and may electrically couple the I/O node to a power supply voltage through an electrical resistance in order to reduce signal reflections within the transmission line.
In one embodiment, the output driver and the input sections of the I/O driver circuit are responsive to periodic transitions in the clock signal from a first voltage level to a second voltage level, wherein the second voltage level is greater than the first voltage level (i.e., rising edges of the clock signal). An output delay time is required for the output driver section to drive the output data signal upon the input/output node, and a propagation delay time is required for a signal to travel from one end of the transmission line to the other. In order for the output data signal driven upon the transmission line by one communication device to reach the other communication device within the first portion of the clock signal period, the first portion of the clock signal period must be greater than or equal to the sum of the output delay time of the output driver section and the propagation delay time of the transmission line.
The input section may require an input xe2x80x9csetupxe2x80x9d time immediately before each rising edge of the clock signal during which the input signal must be substantially constant at the I/O node. The setup time must be observed in order for the input section to produce the correct input data signal. In this case, the remainder of the clock signal period must be greater than or equal to the setup time of the input section. In addition, the period of the clock signal must be greater than or equal to the sum of the output delay time of the output driver section, the propagation delay time of the transmission line, and the setup time of the input section.
The input section may also require an input xe2x80x9choldxe2x80x9d time immediately following the rising edge of the clock signal during which the input signal must be substantially constant at the I/O node. Like the setup time, the hold time must be observed in order for the input section to produce the correct input data signal. In this case, the output delay time of the output driver section must be greater than the hold time of the input section. In addition, in order for the input signal to be substantially constant at the I/O node during the setup and hold times of the input section, the propagation delay time of the transmission line must be greater than the sum of the remainder of the clock signal period and the hold time of the input section.
The present method for achieving simultaneous bidirectional data transmission includes coupling first and second communication devices to opposite ends of a transmission line. The first and second communication devices are configured to operate in response to a periodic clock signal, and to simultaneously: (i) drive an output data signal upon the transmission line during a first portion of a period of the clock signal, and (ii) receive an input data signal from the transmission line during a remainder of the period of the clock signal. Again, the communication devices may be coupled to receive the clock Signal via a clock signal line, or may include circuitry to generate and synchronize two separate clock signals.
The output driver section of the I/O driver circuit may include driver control logic, a first and second switching elements coupled to the I/O node, a first electrical resistance coupled between the first switching element and a first power supply voltage (e.g., VDD), and a second electrical resistance coupled between and the second switching element and a second power supply voltage (e.g., VSS). The driver control logic may receive the output data signal and the periodic clock signal, and may produce a first and second control signals. The first switching element may be coupled to receive the first control signal, and may electrically couple the I/O node to the first power supply voltage through the first electrical resistance in response to the first control signal. The second switching element may receive the second control signal, and may electrically couple the I/O node to the second power supply voltage through the second electrical resistance in response to the second control signal. The driver control logic may generate the first and second control signals such that the first and second switching elements: (i) drive the output data signal upon the I/O node during the first portion of the clock signal period, and (ii) electrically couple the I/O node to the first power supply voltage through the first electrical resistance during the remainder of the period of the clock signal.
The driver control logic may include timing logic which receives the periodic clock signal and produces an output signal which is asserted for the first portion of the period of the clock signal. The timing logic may be triggered by the periodic rising edges of the clock signal. The driver control logic may generate the first and second control signals in response to the timing logic output signal such that the first and second switching elements: (i) drive the output data signal upon the I/O node when the timing logic output signal is asserted, and (ii) electrically couple the I/O node to the first power supply voltage through the first electrical resistance when the timing logic output signal is deasserted.
The input section of the I/O driver circuit may include a differential amplifier and a memory element. The differential amplifier may have a first input terminal receiving the input signal from the I/O node, and a second input terminal receiving a reference voltage. The differential amplifier may produce an output signal dependent upon a voltage difference between the input signal and the reference voltage. The memory element may receive the differential amplifier output signal and the clock signal. During each rising edge of the clock signal, the memory element may store the differential amplifier output signal and provide the output signal as the input data signal at an output terminal.